Verilog For loop : can we synthesis it ? Day 20

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Day21: https://youtu.be/c-yIqm0qiT4 Today's video resources: HDLbits : https://hdlbits.01xz.net/wiki/Main_Page Quora answer : https://www.quora.com/How-is-for-loop-synthesizable-in-any-HDL-Verilog-How-is-it-implemented-in-hardware#:~:text=for%20loop%20is%20a%20synthesizable,is%20synthesised%20by%20the%20tool. Verilog IEEE doc : http://staff.ustc.edu.cn/~songch/download/IEEE.1364-2005.pdfhttps://www.geeksforgeeks.org/magnitude-comparator-in-digital-logic/ Comparator circuit :

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