Learn VERILOG for VLSI Placements for FREE | whyRD

A realistic approach for learning Verilog in 30 days

This video resources :

Verilog Sample questions/concepts: http://www.asic.co.in/Index_files/verilog_interview_questions.htm http://www.asic-world.com/verilog/questions.html https://nandland.com/uart-serial-port-module/ Verilog nptel :https://www.youtube.com/watch?v=FWE0-FOoE4s&list=PLUtfVcb-iqn-EkuBs3arreilxa2UKIChl

How much coding do you need:https://youtu.be/Kz5WxonrS5g

Practice Verilog for free: HDLbits : https://hdlbits.01xz.net/wiki/Main_Page

Bonus Resource: Quora profile of Palash: https://www.quora.com/profile/Palash-Khandale-%E0%A4%AA%E0%A4%B2%E0%A4%BE%E0%A4%B6-%E0%A4%96%E0%A4%82%E0%A4%A1%E0%A4%BE%E0%A4%B3%E0%A5%87

Watch Next: VLSI Design EDA for free :https://youtu.be/G2dUd97IAgc Best 10 Free VLSI courses: https://youtu.be/dnEqRj_GH3Q Ingredient for strong VLSI CV: https://youtu.be/QiGP9saq_yY How Much coding did a VLSI engineer need: https://www.youtube.com/watch?v=Kz5WxonrS5g VLSI future of workplace: https://youtu.be/hyT91uPrX0c VLSI vs PSU: https://youtu.be/fcHATsZTQac VLSI front end vs back end: https://www.youtube.com/watch?v=8iY0kD36xAw Best 10 VLSI courses: https://www.youtube.com/watch?v=dnEqRj_GH3Q Will automation will kill VLSI: https://youtu.be/4Z2haYhNbHc

You need just 30 days to learn the language of VLSI design, a must for all front-end digital profile jobs and also a must-know domain for all VLSI engineers.

About myself: Hi, I am Rajdeep Mazumder, I did my MTech from IIT Delhi in Radiofrequency design and technology. Presently I am working as a hardware engineer with Intel. I am an engineering enthusiast and daily meditator and want to build hardcore engineering teaching as my profession. follow me on LinkedIn- https://www.linkedin.com/in/rajdeep-mazumder instagram- https://www.instagram.com/rajdeep.jgd

Time Stamps 00:00. Is 30 days enough for Verilog ? 00:39 Video contents 01:21 Why Verilog is different? 02:10 Day 1-5 Revision 04:45 What does learning Verilog mean? 05:52 Day 6-16 Verilog Learning Resources 07:04 Day 17-30 Practise Verilog (with Demo) 13:50 Previous year VLSI Interview Questions 14:57 Bonus Resources

Disclaimer: All the views and information shared in this video are as of my best knowledge but please counter-verify all information again. Here I am representing myself only. All the Guest have their own responsibility for any view taken forward on this platform. I made all my effort to share only the information which is already publicly available. No confidential information is being shared. #whyRD #VLSI #verilog ... https://www.youtube.com/watch?v=vRSY6S03EFg