Video Display Generation: The Master Raster Counters

A new series about designing a video display controller for embedded systems implemented on FPGAs or using FPGAs for video generation.

In this series we focus on designing a video display controller for memory constrained systems with focus on being able to generate video comparable with HD TV standards. Including 1080p60, 720P60, 1080P30 with relaxed resolution standards to reduce data throughput and timing constraints. ... https://www.youtube.com/watch?v=g6_7z1BB8Fg