VHDL:tutorial: Part 03: Structural VHDL

Codes:

-- Company: Cisco -- Engineer: Alireza Saberi

library IEEE; use IEEE.STD_LOGIC_1164.ALL; --structural multiplexer of 2-to-1 entity struct_mux is port( In_0,In_1 : in bit; Select_input: in bit; Output: out bit ); end struct_mux;

architecture structural of struct_mux is -- introducing components --Three components --C1 component and2_gate is port( I_0,I_1 : in bit; O: out bit); end component;

--C2 component or2_gate is port( I_0,I_1 : in bit; O: out bit); end component;

--C3 component not_gate is port( I_0 : in bit; O: out bit); end component;

-- introducong signals signal a,b,not_sel : bit;

-- introducong units --There are four units for unit1: or2_gate use entity work.or2_gate(normal); for unit2: and2_gate use entity work.and2_gate(normal); for unit3: and2_gate use entity work.and2_gate(normal); for unit4: not_gate use entity work.not_gate(normal);

begin -- defining interconnection of different units unit1: or2_gate port map (a,b,Output); unit2: and2_gate port map (In_0,not_sel,a); unit3: and2_gate port map(Select_input,In_1,b); unit4: not_gate port map(Select_input,b);

end structural;

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