It all goes wrong! - Making an 8 Bit pipelined CPU - Part 38

The plan for this video was to implement the bus logic for assert/load from the 16 bit transfer bus. I expected to get as far as implementing the 16bit register move instructions. Things went a bit wrong though, the build started to exhibit some off behaviour.

I suspected that I was driving to many logic lines from the clock so worked around that but their were other issues. I left the 16 bit bus control partially done (it's built but not interfaced to anything). The troubleshooting will continue in the next video. ... https://www.youtube.com/watch?v=cnt30vAguGc