16 Bit Transfer Bus Control - Making an 8 Bit pipelined CPU - Part 40

This is a direct continuation of part 38 (The bit before it all went wrong). The control lines for assert/load for the transfer bus are connected back to pipeline stage 1. It's good to be back to adding functionality. The 16 bit registers are going to be easier to work with once the Transfer register has been built, that will need to come soon.

I knew this one could be very short so I took the opportunity to simplify the logic surrounding constant loads, it saved a logic chip in the fetch unit.

Feedback Request: I borrowed a far better microphone to see if it was worth the upgrade, is the sound better? ... https://www.youtube.com/watch?v=Z6tcfjGUcIw