Logic Gates Pulse Width Limiter

In this video Gregory will design a logic gate pulse width limiter with you. The circuit designed can limit a pulse width between MIN and MAX limits.

This circuit uses two parallel monostable pulse generators in a concurrent topology. The input pulse width will be limit so the output never has a width lower than MIN and higher than MAX.

A design optimization is show to reduce gate sizes and the final circuit uses only a 74HC74 and a 74HC132 with some passives.

00:22 - Circuit show up 01:48 - Working principle overview 02:35 - Monostable MAX width limiter 04:43 - Monostable MIN width limiter 07:00 - Full circuit explanation 08:40 - Circuit optimizations

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